Most electrical circuits today, which may be IC devices or embedded sub-circuits within IC devices, are tested using parallel scan path approaches whereby the parallel scan paths are used to input and apply test stimulus patterns to a circuit's combinational logic and to capture and output test response patterns from the circuit's combinational logic.
FIG. 1 illustrates a conventional example of a circuit's 100 combinational logic 102 being tested via parallel scan paths 1-n 104. As previously mentioned, circuit 100 could be an IC or an embedded sub-circuit within an IC. Each scan path 1-n has a scan input (SI-1-n) 106 and a scan output (SO-1-n). Each scan path 1-n is also coupled to a scan enable (SEN) input 110 and to a scan clock (SCK) input 112. The SEN and SCK inputs cause the scan paths 1-n to; (1) input stimulus bit streams 122 during each stimulus input shift cycle 114 to be applied as stimulus 116 to the combinational logic, (2) capture the resulting response 118 from the combinational logic, and (3) shift the captured response data out as response bit streams 124 during each response output shift cycle 120. The structure and operations of the parallel scan paths of FIG. 1 are well known.
FIG. 2 illustrates a typical arrangement between a scan tester 200 and a circuit 100 within an IC 200 that is to be scan tested. Typical scan testers comprise a stimulus data memory 204 for storing stimulus patterns 114 to be input to circuit 100 via SI-1-n, an expected data memory 206 for storing the expected data (ED-1-n) patterns from circuit 100, a compare pass/fail circuit 208 for comparing the expected data from expected data memory 206 against the response patterns 120 output from circuit 100 via SO-1-n, and a controller circuit 210 to control the operation of the stimulus data memory, response data memory, compare pass/fail circuit, and the SCK and SEN inputs to circuit 100 via bus 212.
During test, the controller circuit 210 operates the SCK and SEN inputs to circuit 100 to shift in stimulus bit streams 122 during each shift cycle 114 via SI-1-n, capture response data 118 from combinational logic 102 of circuit 100, and shift out response bit streams 124 during each shift cycle 120 via SO-1-n. Each bit in the response bit stream 124 is compared to an expected data bit from the expected data memory 206. The compare pass/fail circuit is controlled by the SCK and SEN signals to allow it to operate in synchronicity with circuit 100 to allow it to know when to compare the response bits against the expected data bits. The compare pass/fail circuit 208 may be simple or complex. A simple compare pass/fail circuit 208 may simply detect and log the first mismatch between the response bits output from circuit 100 and the expected data bits output from the expected data memory 206. However, a complex compare pass/fail circuit 208 may detect and log all mismatches between the response bit outputs from circuit 100 and the expected data bits output from the expected data memory 206. Further, the more complex compare pass/fail circuit 208 may include the ability to mask off certain compare operations between response bits and expected data bits during the test. At the end of test, the controller circuit 210 accesses the compare pass/fail circuit, via bus 212, to obtain pass/fail information.
The stimulus data memory 204 and expected data memory 206 of tester 200 may need to be very large. For example, circuit 100 may contain 32 scan paths 104 each being 50,000 bits long. In this example, the stimulus data memory 204 needs to store 50,0000 32-bit wide stimulus bit patterns to be input to circuit 100 during each shift cycle 114 operation, and the expected data memory 206 needs to store 50,0000 32-bit wide expected data bit patterns to match against the response bit patterns output from circuit 100 during each shift cycle operation. Assuming 10,000 shift cycle operations are required for the test, the memories 204 and 206 would each need to be able to store 500 million 32-bit patterns. Additionally, memories 204 and 206 would need to be fast memories to allow operating the shift operations at high SCK rates to reduce the shift cycle times during test. The need for large high speed stimulus and expected data memories increases the cost of scan testers 200, which is reflected in the selling cost of the IC to the customer.